Yu-Wei Fan’s Personal Website

News

• April 2026: Our paper Interplay of Efficient Model Checking and Secure Processor Design: A Case Study on Secure Speculation was accepted to S&P 2026.
• February 2026: Our paper Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping was accepted to DAC 2026.
• December 2025: Our paper SecIC3: Customizing IC3 for Hardware Security Verification was accepted to DATE 2026.
• July 2024: Our paper 2-DQBF Solving and Certification via Property-Directed Reachability Analysis was accepted to FMCAD 2024.

Short Biography

I am a second-year ECE PhD student at Princeton University advised by Prof. Sharad Malik. I received my B.S. and M.S. from National Taiwan University (NTU). During my Master’s study, I was advised by Prof. Jie-Hong Roland Jiang on decision procedures and electronic design automation (EDA).

I am broadly interested in automated reasoning, formal verification, and hardware security.